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[Post-TeleCom sofeware systems] cordic_v1.0.4

Description: Altera公司的CORDIC开发包，用Verilog编写的，安装在Quartus相同目录中，里面有详细的开发说明。-Altera
Platform: | Size: 1355776 | Author: YangJun | Hits:

[VHDL-FPGA-Verilog] sditest

Description: 基于ep3c25的altera sdi ip核的使用，串并转换和并串转换-Ep3c25 based on the altera sdi ip nuclear use, and conversion and string and string conversion
Platform: | Size: 1477632 | Author: 林丹 | Hits:

[VHDL-FPGA-Verilog] altera_up_avalon_ps2

Description: 花了半个月才改好的Atera DE1/DE2 ps2 IP 驱动核。放在FPGA工程目录下可以直接使用。本IP能够驱动PS/2键盘和鼠标。使用时只要调用HAL目录下的文件即可以直接使用！-Spent a good two weeks we have made some changes Atera DE1/DE2 ps2 IP-driven nuclear. On the FPGA project directory can be used directly. The IP to drive PS/2 keyboard and mouse. When used as long as the call HAL directory file that can be used directly!
Platform: | Size: 27648 | Author: 王乔 | Hits:

[VHDL-FPGA-Verilog] DM9000A

Description: Verilog 编写的网卡DM9000A的IP核，altera公司寄的DE2系统中的源程序核-Verilog prepared DM9000A the IP core network card, altera company sent DE2 System source of nuclear
Platform: | Size: 16384 | Author: zhyy | Hits:

[Embeded-SCM Develop] i2c_p

Description: I2C IP，可以直接用，有相关规范文档说明-I2C IP, can be directly used, have the relevant normative document explains
Platform: | Size: 2207744 | Author: pantree | Hits:

[VHDL-FPGA-Verilog] CF_card_base_on_NiosII

Description: 基于NIOS的CF卡应用(包括了软件和硬件),ALTERA的IP库中只提供了底层的硬件寄存器描述头文件.这是个基于IP核HAL的软件,以及相应的硬件设计示例.-NIOS based on the CF card applications (including the software and hardware), ALTERA the IP library provides only the bottom of the first document describes the hardware registers. This is a HAL-based IP core of the software, hardware design and the corresponding sample.
Platform: | Size: 1398784 | Author: 沈阳 | Hits:

[VHDL-FPGA-Verilog] hgb_pci_host

Description: 内有一PCI 主 和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持： 1、 对目标PCI_T进行配置； 2、 对目标进行单周期读写； 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的-There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of
Platform: | Size: 2712576 | Author: | Hits:

[Windows Develop] SimpleMSN

Description: 自己写的即时通信软件，包含客户端/服务器端，采用广播模式通信，可以由一个服务端连接多个客户端（可以指定多个iP），服务端发送确认信息并在客户端弹出提示信息，然后开始由服务端单向通信。将类似MSN的提示框封装为DLL,在客户端程序中调用。VC6编译通过，适合做二次开发。-Write their own real-time communication software, including client/server-side, using radio communication mode, you can connect from a service multiple clients (You can specify multiple iP), services client to send confirmation message and the client pop-up message , and then started by the end of a one-way communication services. MSN will be a similar package for the prompt box DLL, the client program to call. VC6 compiler passed, suitable for secondary development.
Platform: | Size: 1830912 | Author: 陈文捷 | Hits:

[Software Engineering] 15Altera_IP

Description: 里面包含15个altera的IP核的源代码,包括I2C，UART，VGA_SYN-Which contains 15 nuclear altera the IP source code, including I2C, UART, VGA_SYN
Platform: | Size: 49152 | Author: hhl | Hits:

[VHDL-FPGA-Verilog] uart_regs

Description: uart_regs core目录下为Altera的IP宏功能模块-Altera IP uart_regs core
Platform: | Size: 941056 | Author: 寻宝人 | Hits:

[VHDL-FPGA-Verilog] Project

Description: 熟悉Altera IP的产生和实现方法定制一个8B10B编码器- 8B10B codeer
Platform: | Size: 160768 | Author: 寻宝人 | Hits:

[VHDL-FPGA-Verilog] Altera_8051_IPcore_v1.2

Description: Alera 的8051 IP core的示例文件5个-Alera the 8051 IP core of the sample file 5
Platform: | Size: 1884160 | Author: zheng | Hits:

[VHDL-FPGA-Verilog] IPcore

Description: 基于EP3C25的Altera SDI IP核的使用-EP3C25 Altera SDI IP
Platform: | Size: 1486848 | Author: wzk | Hits:

[VHDL-FPGA-Verilog] PWM_LED

Description: 基于ALTERA公司NIOSII的LED灯控PWM IP核设计-ALTERA-based company controlled NIOSII the LED lamp PWM IP-core design
Platform: | Size: 10481664 | Author: 王超 | Hits:

[Other] DDC

Description: Digital Down Covertor Documents
Platform: | Size: 1491968 | Author: Kiran | Hits:

[VHDL-FPGA-Verilog] FFTVHDl

Description: 基于FPGA的fft实现 摘要：本系统基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核，代替传统DSP芯片或高性能单片机，实现了基于FFT的音频信号分析。-FPGA-based realization of the fft Abstract: This system is based on Altera Cyclone II family of embedded high-performance FPGA embedded IP core (Nios) soft-core processor, chip or replace the traditional high-performance single-chip DSP to realize the audio signals based on FFT analysis .
Platform: | Size: 32768 | Author: xiang | Hits:

[VHDL-FPGA-Verilog] SRAM_Controller

Description: Altera University Program的Avalon总线IP核，SRAM控制代码，可以解压后直接挂载在Avalon总线上 -Altera University Program of the Avalon bus IP core, SRAM control code can be directly mounted after decompression in the Avalon bus
Platform: | Size: 324608 | Author: vicky | Hits:

[VHDL-FPGA-Verilog] vhdl-MIPS

Description: Quartus-Altera Nios... VHDl based, complete MIPS implementation, document, flowcharts plus code
Platform: | Size: 4330496 | Author: ak | Hits:

[VHDL-FPGA-Verilog] Guagle_wave

Description: altera 的存储器IP核的初始化mif文件生成器，可任意点数和任意波形-Initial altera s ip core of ROM or RAM need .mif file,use this software you can generate it ,any wave
Platform: | Size: 216064 | Author: chenlei | Hits:

[VHDL-FPGA-Verilog] FFT_verilog

Description: verilog实现的FFT变换，经硬件测试其功能与Altera的FFT IP核相近-verilog implementation FFT transform, through hardware, test its functionality with Altera' s FFT IP core similar to
Platform: | Size: 618496 | Author: culun | Hits:
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